This editorial introduces the special section on ARC 2025 Journal Track, comprising extended versions of five selected articles from the 2025 Int.l Symp. on Applied Reconfigurable Computing (ARC), together with a perspective article commemorating the first 20 years of the symposium. The selected contributions illustrate the breadth of contemporary reconfigurable computing research and address key challenges in compilation, dependable acceleration,  low-latency machine learning, on-chip communication, and event-driven edge intelligence. Specifically, they investigate control-flow-aware compilation for coarse-grained reconfigurable arrays; rapid detection and recovery from radiation-induced faults in FPGA-based AI accelerators; streamlined dataflow architectures for echo state networks; throughput-adaptive networks-on-chip for AI accelerators; and hardware-accelerated graph neural networks for event-based audio processing. The anniversary article complements these works by reviewing representative research themes developed across 2 decades of ARC and identifying emerging directions for the field. Collectively, the articles demonstrate the continuing importance of cross-layer approaches that combine algorithms, compilation, architectures, runtime mechanisms,  and application-specific optimization to improve the performance, energy efficiency, programmability, and dependability of reconfigurable systems.